{"created":"2023-07-27T04:53:39.231989+00:00","id":66923,"links":{},"metadata":{"_buckets":{"deposit":"5ded49c1-eaa6-41ca-87dd-36c0875373d1"},"_deposit":{"created_by":3,"id":"66923","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"66923"},"status":"published"},"_oai":{"id":"oai:tohoku.repo.nii.ac.jp:00066923","sets":["81:219"]},"author_link":["159565","159563","159566","159564"],"item_2_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1998","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"195, 437","bibliographicPageStart":"194","bibliographic_titles":[{"bibliographic_title":"1998 IEEE International Solid-State Circuits Conference : digest of technical papers"}]}]},"item_2_date_62":{"attribute_name":"登録日","attribute_value_mlt":[{"subitem_date_issued_datetime":"2010-04-21","subitem_date_issued_type":"Created"}]},"item_2_date_63":{"attribute_name":"公開日（投稿完了日）","attribute_value_mlt":[{"subitem_date_issued_datetime":"2010-04-21","subitem_date_issued_type":"Created"}]},"item_2_date_65":{"attribute_name":"発行日","attribute_value_mlt":[{"subitem_date_issued_datetime":"1998","subitem_date_issued_type":"Created"}]},"item_2_date_80":{"attribute_name":"更新日","attribute_value_mlt":[{"subitem_date_issued_datetime":"2010-04-21","subitem_date_issued_type":"Created"}]},"item_2_description_15":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_41":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"学術論文 (Article)","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用)","subitem_description_type":"Other"}]},"item_2_description_66":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"988157 bytes","subitem_description_type":"Other"}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"159563","nameIdentifierScheme":"WEKO"}],"names":[{"name":"羽生, 貴弘"}]}]},"item_2_publisher_34":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers"}]},"item_2_radio_69":{"attribute_name":"公開範囲","attribute_value_mlt":[{"subitem_radio_item":"学外"}]},"item_2_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1109/ISSCC.1998.672432","subitem_relation_type_select":"DOI"}}]},"item_2_relation_8":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"0-7803-4344-1","subitem_relation_type_select":"ISBN"}}]},"item_2_select_78":{"attribute_name":"大学情報DBリポジトリ区分","attribute_value_mlt":[{"subitem_select_item":"許諾"}]},"item_2_version_type_16":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hanyu, T."}],"nameIdentifiers":[{"nameIdentifier":"159564","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Teranishi, K."}],"nameIdentifiers":[{"nameIdentifier":"159565","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Kameyama, M."}],"nameIdentifiers":[{"nameIdentifier":"159566","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-02-22"}],"displaytype":"detail","filename":"10.1109-ISSCC.1998.672432.pdf","filesize":[{"value":"988.2 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"10.1109-ISSCC.1998.672432.pdf","url":"https://tohoku.repo.nii.ac.jp/record/66923/files/10.1109-ISSCC.1998.672432.pdf"},"version_id":"de89326f-ace6-4d5a-9baf-fd7e20da2617"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network"}]},"item_type_id":"2","owner":"3","path":["219"],"pubdate":{"attribute_name":"公開日","attribute_value":"2010-04-21"},"publish_date":"2010-04-21","publish_status":"0","recid":"66923","relation_version_is_last":true,"title":["Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-07-27T17:28:54.159769+00:00"}